Mechanical cooling fin for interconnects

ABSTRACT

In one embodiment, an integrated circuit includes an electrically active interconnect line within a dielectric layer having a top and bottom surface, the bottom surface of the dielectric layer being coupled to the top surface of a substrate underlying the dielectric layer. The dielectric layer has horizontally arranged heat dissipating layers. An electrically inactive conductor or cooling fin is located within the dielectric layer at a heat dissipating layer below and closer to the substrate than said active interconnect line. The electrically inactive conductor is coupled to said electrically active interconnect line as an extensions of electrically active interconnect line to dissipate heat therefrom.

FIELD OF INVENTION

[0001] This invention relates to integrated circuits and moreparticularly to an integrated circuit providing thermally conductiveelectrically inactive extensions to active interconnect lines to reducelocalized Joule heating in interconnect lines.

BACKGROUND OF INVENTION

[0002] Typical semiconductor devices comprise multiple circuits formedwithin a dielectric region comprised of one or more dielectric layers ontop of a silicon substrate or wafer. On top of the substrate are layersof dielectric and layers of metal and layers of metal embedded indielectric. When the metal interconnect leads of the circuits are ondifferent layers, conductive vias extend through the dielectric layersto make connections between the wiring leads on different interconnectlevels. Sometimes, based on the circuit design, a significantly largeamount of current may flow through the metal interconnect lead, causingJoule heating to increase the temperature of the metal lead. The currentflowing through these leads may cause sufficient Joule heating toincrease the temperature of the lead. Such temperature increases mayaccelerate reliability wearout mechanisms such as eletromigration andstress migration that might possibly lead to failure of the integratedcircuit. It is common practice to widen leads that have currentdensities in excessive of those required for reliable operation.However, widening leads may have a deleterious impact on the area of theintegrated circuit.

[0003] Current trends in integrated circuit design include usingdielectric materials of increasingly low thermal conductivity,exacerbating the deleterious effects of Joule heating within theintegrated circuit. In addition, as integrated circuit technologies arescaled, the number of layers of metal interconnect is increasing, makingit increasingly difficult to dissipate heat from metal leads.Furthermore, integrated circuits that draw relatively large amounts ofpower may intensify the increases in temperature in the integratedcircuit due to Joule heating effects.

[0004] During fabrication of integrated circuits, dummy metal structuresmay be inserted in the integrated circuit to increase the density ofmetal structures on the top surface of the integrated circuit. Forexample, insertion of dummy metal structures may lead to improvedpattern consistency of metal leads and to reduced “dishing” duringchemical mechanical polishing (CMP) of the integrated circuit. It iscommon practice to use dummy metal structures during the fabrication ofintegrated circuits. Because metals are much better thermal conductorsthan are dielectrics, the presence of dummy metal structures surroundingregions where the temperatures of metal leads may become excessive cancontribute to heat flow away from such interconnect region toward heatsinking regions, thereby resulting in lower temperatures of the metalleads. Vertical vias may be formed within the dielectric layer betweendummy metal structures and filled with a thermally conductive materialto provide direct thermal connections between dummy metal structures.Although this may help dissipate heat from metal leads or other heatgenerating structures, such techniques may still be inadequate forintegrated circuit applications. An integrated circuit with such heatconductive structures is described in co-pending patent application ofHunter et al. entitled “Integrated Circuit Providing ThermallyConductive Structures Substantially Horizontally Coupled To One AnotherWithin One or More Heat Dissipation Layers To Dissipate Heat From A HeatGenerating Structure”, serial no. (TI-33209) filed Dec. 20, 2002. Thisapplication is incorporated herein by reference.

SUMMARY OF INVENTION

[0005] According to an embodiment of the present invention, electricallyinactive extensions of electrically active interconnect leads arefabricated. The term electrically inactive as used herein means thatthey are not connected to anything else, and therefore do not conductany nominal current. The purpose of these electrically inactiveextensions are to more efficiently conduct heat to regions of theintegrated circuit design where heat can flow to heat sinking regions ofthe integrated circuit, such as the substrate upon which the integratedcircuit is fabricated. Each extension can be thought of as amicro-miniature thermal cooling fin. The position of each thermalcooling fin can be optimized with respect to it size and nearness to thesubstrate and to other dummy metal structures.

DESCRIPTION OF DRAWINGS

[0006]FIG. 1 illustrates a top plan view of embodiments described inconnection with FIGS. 2-7 of the present invention of an electricallyactive line and an electrically inactive cooling fin.

[0007]FIG. 2 illustrates a cross section of FIG. 1 taken through A-A forone embodiment of the present invention.

[0008]FIG. 3 illustrates a cross section of FIG. 1 taken through B-B forthe embodiment of FIG. 2.

[0009]FIG. 4 illustrates a cross section taken through A-A of FIG. 1wherein the electrically inactive cooling fin is positioned multiplelayers below the electrically active line.

[0010]FIG. 5 illustrates a cross section taken through B-B of FIG. 1wherein the electrically inactive cooling fin is positioned multiplelayers below the electrically active line.

[0011]FIG. 6 illustrates a cross section view of FIG. 1 taken throughA-A wherein the cooling fin is on the on the same surface as the via inFIGS. 2 and 3.

[0012]FIG. 7 illustrates a perspective view of the case where themechanical cooling fin is in the shape of an “H” and is in the same heatdissipating layer as the via In FIG. 2 and 3 for a single damasceneprocess.

[0013]FIG. 8 illustrates a top plan view of an embodiment described inconnection with FIGS. 9-10 of the present invention of an electricallyactive line and an electrically inactive cooling fin with dummy metalstructures.

[0014]FIG. 9 illustrates a cross section taken through A-A of FIG. 8wherein the dielectric region contains layers of dummy metal and theelectrically inactive cooling fin is aligned to overlay on top ofunderlying dummy metal in accordance with another embodiment of thepresent invention.

[0015]FIG. 10 illustrates a cross section taken through B-B of FIG. 8wherein the dielectric region contains layers of dummy metal and theelectrically inactive cooling fin is aligned to overlay on top ofunderlying dummy metal in accordance with the same embodiment of thepresent invention as FIG. 9.

DESCRIPTION OF PREFERRED EMBODIMENT

[0016] FIGS. 1-3 shows one embodiment of the present invention forreducing the temperature rise due to Joule heating. FIG. 1 is a top planview of the integrated circuit 10 according to embodiments of thepresent invention described in connection with FIGS. 2-7. FIG. 2 is across section taken through A-A in FIG. 1 and FIG. 3 is an orthogonalcross section taken through B-B in FIG. 1. The integrated circuit 10includes a substrate 24 of silicon, for example, having a top surface 26and bottom surface 28 and dielectric region or layer 18 above thesubstrate 24 with a bottom surface 22 adjacent with the top surface 26of the substrate 24. The dielectric region or layer 18 may includesilicon dioxide, silicon nitride, or other suitable dielectric material.The dielectric region or layer 18 comprises multiple layers of heatgenerating leads or other structures embedded within the dielectricregion 18, such as an electrically active current carrying metal lead 13in layer 18 a. The metal lead 13 is represented by dashed lines in FIG.1 since the lead 13 is in a layer 18 a below the top surface of thedielectric. The heat generating electrically active current carry metallead may include copper, aluminum tungsten, or other suitable metal ormetal alloy. The dielectric region 18 has at least one of its twosurfaces—top and bottom—thermally coupled to an external heat sink byvirtue of its packaging details. For simplicity, we will refer to thecase where heat flow is through the bottom surface 22 connection to theintegrated circuit substrate 24 at the top surface 26, although it isunderstood that the invention applies to the case where the other orboth surfaces are thermally coupled to heat sinks. There should beexternal heart sinks, as part of the details of integrated circuitpackaging and the mounting of packages in the systems.

[0017] In accordance with one embodiment of the present inventionthermal cooling conductor or fin 14 is located in a substantiallyhorizontal region 17 a in the dielectric region 18 below an interconnectconnector 13 layer 18 a. This cooling fin is represented by dashed linesin FIG. 1 since this is also below the top surface. The cooling fin 14is physically connected to the electrically active interconnectconductor 13 to help dissipate the heat generated in the electricallyactive interconnect conductor 13. The thermal cooling conductor or fin14 includes electrically inactive metal conductor such as a straightheat conductive line 14 physically connected by a connecting conductorvia 15 extending in layer 18 b between layers 18 a and 17 a to theelectrically active interconnect lead 13 in which Joule heat is beinggenerated. Only a portion of the electrically active interconnect lead13 is shown in the FIGS. 1-3.

[0018] The electrical inactivity of cooling fin 14 means that it is notconnected to any other portion of electrically active interconnect, andtherefore does not carry any intentional current. It is also to beunderstood that the shape of the cooling fin 14 does not have to be astraight line. It is also to be understood that the cooling fin 14 doesnot have to be constrained to a specific size. It can be any shape andsize that is convenient while considering the tradeoffs between impacton circuit layout, circuit performance, and thermal management.

[0019] This above described arrangement is a preferred embodimentbecause it places the cooling fin 14 as close as possible to the heatsinking substrate 24, thereby optimizing heat loss from the activemetal. Alignment with other electrically inactive metal structures, suchas dummy metal, may also optimize heat loss and consequent temperaturereduction.

[0020] In the case where the dominant heat sink direction is above thedielectric region 18 or for other reasons, the electrically inactivecooling fin 14 would be in a layer above the electrically activeinterconnect 13 and the placement of the elements in FIGS. 1-3 would bereversed with fin 14 closer to the top of the dielectric region 18 wherethe top heat sink is located in place of active interconnect 13 and thelocation of the interconnect line 13 would be below the and in place offin 14 in FIGS. 2 and 3.

[0021] In general, the electrically active interconnect lead can beconnected to a cooling fin which is on ant level above or below. Whetherit is above or below depends on whether the dominant heat sinkingdirection is above or below the dielectric region 18, respectively. Asan example, in the case where the dominant heat sinking direction isthrough the substrate 24, there may be multiple vias 15 between theelectrically active interconnect lead 13 and the inactive cooling fin 14as illustrated in FIGS. 4 and 5. FIGS. 4 and 5 are cross sections ofFIG. 1 taken at planes A-A for FIG. 4 and plane B-B for FIG. 5. Theconnection between the two vias 15 may include a conductive pad or block17 at layer 18 a. The closer the cooling fin 14 can be placed to theheat sinking substrate 24 for example the more optimal will be thetemperature reduction of the electrically active lead. If on the otherhand the heat sinking surface is at the top, the closer to the top thebetter.

[0022] In accordance with another embodiment of the present invention,the electrically inactive heat dissipating cooling fin 14 is built inthe same layer 18 b as was the via 15 in FIG. 1-3, by extending thenormal via pattern to have an extended via shape. This is illustrated inFIG. 6 for the case where the electrically inactive cooling fin 14 isbelow the electrically active interconnect lead 13 in the same plane asthe via 15 in FIGS. 1-3. FIG. 6 illustrates the A-A cross section ofFIG. 1. The thermal cooling fin 14 may be formed in the surroundingdielectric layer 18 b during the same single damasene process as is thevia 15 in FIGS. 1-3, wherein holes are formed in the surroundingdielectric layer 18 b and filled with copper and then polished off tothe surface of the dielectric layer. It is to be understood that thecooling fin 14 could also have been fabricated above the electricallyactive interconnect lead 13.

[0023] The shape of the cooling fin 14 may be other than a straight lineand as shown by the perspective view in FIG. 7 to provide the coolingsurface. Any shape consistent with via design rule constraints could bepatterned. In FIG. 7 the electrically inactive cooling fin 14 extendsout in the shape of an “H” with two conductors 14 a and 14 b parallel tothe interconnect line 13 and a cross connective and conductive bar 14 corthogonal and connected to conductors 14 a and 14 b, with the cross bar14 c across the interconnect lead 13 and connected thereto. Heat flowfrom the line 13 to the fin occurs in the overlap region between theline 13 and the crossbar 14 c, where the two layers are in contact. Theextension of the interconnect line 13 in FIG. 7 is not solid so as toillustrate the fin 14.

[0024] In accordance with another embodiment of the present invention,the electrically inactive heat dissipating cooling fin 14 is built inthe same layer as the electrically active interconnect line 13 and is infact a heat dissipating stub connection off the active line. The shapecan be other than a straight line. extending and fabricated when theinterconnect line is formed. The fins have to be designed so as not tointerfere with the other electrical lines, and in a manner that hasacceptable parasitic capacitance.

[0025] The presence of dummy metal structures increases the conductivityof heat to the substrate 11 and a heat sink. The electrically inactivecooling fin may be lined up with dummy metal structures 33 asillustrated in FIGS. 8, 9 and 10. In FIG. 8 and 9 the electricallyinactive cooling fin 14 extends along several dummy metal structures 33below the cooling fin that aid in the conduction of the heat to thesubstrate 11. In FIG. 8 these dummy metal structures 33 are representedby dashed lines because they are below and aligned with the upper dummymetal structures 30 and the cooling fin 14. In FIG. 10 the electricallyinactive cooling fin 14 is lined up with a dummy metal structure 33 thatis located between the cooling fin 14 and the substrate 11.

[0026] Although the system and method of the present invention has beendescribed in connection with the preferred embodiment, it is notintended to be limited to the specific form set forth herein, but on thecontrary, it is intended to cover such alternatives, modifications, andequivalents, as can be reasonably included within the spirit and scopeof the invention as defined by the appended claims.

In the claims:
 1. A method of dissipating heat in an electrically activeinterconnect line in an integrated circuit comprises the steps of:providing an electrically inactive conductor and connecting said anelectrically inactive conductor to said electrically active interconnectline as an extensions of said electrically active interconnect line todissipate heat therefrom.
 2. The method of claim 1 wherein saidelectrically inactive conductor is on a heat dissipating layer of adielectric region closer to a heat dissipating substrate than saidelectrically active interconnect line.
 3. The method of claim 2 whereinsaid electrically inactive conductor is connected to said electricallyactive interconnect line using one or more vias through one or more heatdissipating layers.
 4. The method of claim 3 wherein said electricallyinactive conductor is connected to said electrically active interconnectline using at least two vias and a conducting pad through two or moreheat dissipating layers.
 5. The method of claim 2 wherein saiddielectric region includes dummy metal structures and said electricallyinactive conductor is aligned with one or more of said dummy metalstructures to aid in dissipating heat from said electrically inactiveconductor
 6. The method of claim 5 wherein said dummy metal structuresis said dielectric region is between said electrically inactiveconductor and said substrate.
 7. The method of claim 2 including thestep of coupling said heat dissipating substrate to a heat sink.
 8. Themethod of claim 2 including the step of connecting said electricallyinactive conductor directly to a heat sink by a via through saiddielectric region.
 9. The method of claim 1 wherein said electricallyinactive conductor is in a straight line.
 10. The method of claim 1wherein said electrically inactive conductor is in not in a straightline.
 11. The method of claim 10 wherein said electrically inactiveconductor is in the shape of an H with two parallel conductors and across connector connected to the electrically active connector.
 12. Themethod of claim 11 wherein said electrically inactive conductor is inthe heat dissipating layer adjacent to said electrically activeconductor and closer to said substrate and wherein said electricallyinactive conductor and the via connection to the electrically inactiveconductor is formed by the damascene process.
 13. An integrated circuit,comprising: an electrically active interconnect line within a dielectriclayer having a top and bottom surface, the bottom surface of thedielectric layer being coupled to the top surface of a substrateunderlying the dielectric layer; said dielectric layer havinghorizontally arranged heat dissipating heat dissipating layers and anelectrically inactive conductor within said dielectric layer at a heatdissipating layer closer to the substrate than said active interconnectline; said electrically inactive conductor coupled to said electricallyactive interconnect line as an extensions of electrically activeinterconnect line to dissipate heat therefrom.
 14. The integratedcircuit of claim 13 wherein said electrically inactive conductor isconnected to said electrically active interconnect line using one ormore vias through one or more heat dissipating layers.
 15. Theintegrated circuit of claim 14 wherein said electrically inactiveconductor is connected to said electrically active interconnect lineusing at least two vias and a conducting pad through two or more heatdissipating layers.
 16. The integrated circuit of claim 14 wherein saiddielectric region includes dummy metal structures and said electricallyinactive conductor is aligned with one or more of said dummy metalstructures to aid in dissipating heat from said electrically inactiveconductor
 17. The integrated circuit of claim 16 wherein said dummymetal structures is said dielectric region is between said electricallyinactive conductor and said substrate.
 18. The integrated circuit ofclaim 13 including means for coupling said heat dissipating substrate toa heat sink.
 19. The integrated circuit of claim 13 including means forconnecting said electrically inactive conductor directly to a heat sinkby a via through said dielectric region.
 20. The integrated circuit ofclaim 13 including means for connecting said electrically inactiveconductor directly to a heat sink by a via through said dielectricregion and said substrate.